| SESSION B : DRAM, SRAM and Soft-Error-Rate |
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| ORAL PRESENTATIONS |
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B-1
14h00 |
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Invited :"DRAM cell trends"
P. Fazan |
B-2
14h30 |
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1T-Bulk DRAM cell with improved performances: the way to scaling
R. Ranica, A. Villaret, P. Malinge, P. Candelier, P. Masson, R. Bouchakour, P. Mazoyer, T. Skotnicki |
B-3
14h50 |
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FinFET based zero-capacitor DRAM (Z-RAM) cell for sub 45 memory generations
S. Okhonin, M. Nagoga, P. Fazan, L. Mathew, B.-Y. Nguen, H.-H. Chen, T. Stephens |
B-4
15h10 |
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Evolution of stacked-capacitor technology for embedded DRAM applications
N. Emonet, N. Jourdan, A. Berthelot, M. Piazza, D. Fraboulet, L. Gabette, C. Caillat, M. Charleux, B. Boeck, J. Regolini, D. Dutartre, V. Huard, F. Monsieur, P. Mazoyer, E. Gerritsen |
15h30 |
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Poster presentation and coffee break |
B-5
16h00 |
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Invited: " Embedded memory design : challenge or nightmare"
J. Hendrickx |
B-6
16h30 |
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A small granular controlled leakage reduction system for SRAMs
P. Geens, W. Dehaene |
B-7
16h50 |
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Impact of process variations on the alpha-particle-induced SER of embedded SRAMs
T. Heijmen, B. Kruseman |
B-8
17h10 |
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High density SRAM robust to radiation-induced soft errors in 90 nm CMOS technology
P. Roche, F. Jacquet, G. Gasiot, C. Caillat, B. Borot, J ;P. Schoellkopf |
| POSTERS |
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BP-1 |
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A model to explain the C-V curve of DRAM capacitors with silicon electrodes and trapping dielectrics
L. Lopez, P. Masson, D. Née, R. Bouchakour |
BP-2 |
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Timed verification of the SPSMALL memory
M. Baclet, R. Chevallier |
BP-3 |
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Device simulation study of SEU in SRAMs based on double-gate MOSFETs
K. Castellani-Coulié, D. Munteanu, J.-L. Autran, V. Ferlet-Cavrois, P. Paillet, P. Masson |
BP-4 |
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A system-level approach for memory robustness
R. Mariani, G. Boschi, A. Ricca |
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