Welcome ICMTD'05

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Scientific Technical committee

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International Conference on
Memory Technology and Design

 

ICMTD’05 –PROGRAM

SESSION F : Memories and high- k dielectrics

ORAL PRESENTATIONS
F-1
9h00
  Use of W damascene as true metal1 in a 130 nm flash technology
S. Louwers

 

F-2
9h20

  Investigation of SiO 2/HfO 2 gate stacks for application to non-volatile memory devices
J. Buckley, B. De Salvo, G. Ghibaudo, M. Gely, J.F. Damlencourt, F. Martin, G. Nicotra, S. Deleonibus
F-3
9h40
  Scaling down the interpoly dielectric for next generation flash memory : challenges and opportunities
B. Govoreanu, D. Brunco, J. Van Houdt
F-4
10h00
  ISSG RTO (In-situ Steam Generation Rapid Thermal Oxidation) grown tunnel oxide on advanced FLOTOX E 2PROM memories
G. Festes, S. Angle, J.-M. Bédrine, M. Berrebi, M. Cerisier, E. Daemen, A. Dumas, M. Grégoire, E. Hugonnard, P. Rohr, E. Serres, A. Solere
10h20
  Poster presentation and coffee break
F-5
10h50
  SONOS flash memories with HfO 2 or HfSiON
R. Van Schaijk, M. Van Duuren, F. Neuilly, W. Baks, A. H. Miranda, M. Slotboom, N. Akil, P.G. Tello
F-6
11h10
 

Fully compatible novel SNONOS structure for improved electrical performance in NAND flash memories
J.H. Han, J.K. Kim, S.H. Lee, S. Jeon, C. Kim

F-7
11h30
  Scaling effects in dual-bit split-gate nitride memory devices
L. Breuil, L. Haspeslagh, M. Lorenzini, J. De Vos, J. Van houdt

F-8
11h50

  Low voltage and low power embedded 2T-SONOS flash memories
M. Slotboom, D. Dormans, M. Van Duuren, R. Van Schaijk, N. Akil, R. Beurze
POSTERS
FP-1
  Retention reliability improvement using nitride with varying trap density in SONOS type non-volatile memory
J.H. Kim, J.H. Han, Y.S. Min, M.K. Kim, Y.S. Jeong, S. Jeon, J.W. Hyun, S.H. Lee, H.S Chae, S.D. Chae, C. Kim
FP-2
  Flash memory with high-k tunnel dielectrics : comparative retention study
P. Blomme, A. Akheyar, J. Van Houdt, K. De Meyer
FP-3
  A 4 MegaBit, 128-bit data embeded flash memory allowing high-speed in place code execution
M. Combe, J.-M. Daga
FP-4
  Lifetime model and procedure for failure rate prediction of moving bits in case of room temperature retention
T. Yao, D. Medjahed, P. Gassot, A. Lowe, P. Cacharelis
FP-5
  EEPROM retention time extrapolation from floating gate SILC measurements
S. Burignat, N. Baboux, C. Plossu, P. Boivin
FP-6
  A new reliable P/E methodology for fully fowler-nordheim operating non volatile memories
F. Irrera, G. Puzzilli
FP-7
  STI engineering for high program & erase performance of STI-bounded nitride storage flash memory cells
M. Isler, J.-M. Schley, S. Riedel, T. Mikolajick, C. Ludwig, K.-H. Kuesters, G. Tempel, J.-U. Sachse, P. Deconinck, R. Mikalo, R. Reichelt, N. Schulse, E. Stein v. Kamienski, M. Strassburg, J. Willer, F. Lau, R. Hagenbeck, P. Haibach
FP-8
  Low temperature postmetallisation annealing of high-k dielectrics
Y.F. Loo, S. Taylor, P. Taechakumput, A.C. Jones, P.R. Chalker, L.M. Smith
FP-9
  EEPROM failure analysis methodology : can progammed charges be measured directly ?
C. De Nardi, R. Desplats, P. Perdu, F. Beaudoin, J.-L. Gauffier
FP-10
  Flash memory cell : an automated diagnosis tool for geometric failures
B. Saillet, J.-M. Portal, D. Née
FP-11
  A novel embedded OTP NVM using standar foundry CMOS logic technology
BM. Fliesler, G. Rosendale, J. Wang, C. Ng, Z.S. Liu, J. Peng