ICMTD’07 – PRELIMINARY PROGRAM |
SESSION F : SRAM & PROCESS VARIABILITY |
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F-1
9h00
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Invited : “Real-time Soft-Error Rate Testing of Semiconductor Memories on the European Test Platform ASTEP”
J.-L. Autran (L2MP-IUF), P. Roche (STMicroelectronics), G. Gasiot (STMicroelectronics), D. Munteanu (L2MP), T. Parrassin (STMicroelectronics), J. Borel (JB R&D), J.P. Schoellkopf (STMicroelectronics)
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F-2
9h20
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Low Voltage SRAM with Noble Cell Bias Technique to Increase Static Noise Margin
Y. Chung, S.H. Song, Y.J. Eom, S.W. Shim (Kyungpook National University)
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F-3
9h40
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A Noise-Margin Monitor for SRAMs
P. Geens, W. Dehaene
(Katholieke Universiteit Leuven)
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F-4
10h00
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A Variability Tolerant Embedded SRAM Offering Runtime Selectable Energy/Delay Figures
H. Wang (IMEC), M. Miranda (IMEC), P. Geens (KUL), W. Dehaene (KUL), F. Catthoor (IMEC)
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10h20 |
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Coffee break
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F-5
10h50 |
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Protection of embedded memory systems - a comprehensive solution
R. Mariani (Yogitech SpA), F. Colucci (Yogitech SpA), P. Fuhrmann (Philips Research Laboratories)
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F-6
11h10 |
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Bit Cell Leakage-Aware SRAM Sense Amplifier Activation Schemes
T. Song (Georgia Institute), K. Lim (Georgia Institute), G. Kim (Samsung), I. Son (Samsung), J. Laskar (Georgia Institute)
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F-7
11h30 |
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A 128Kb 5T SRAM in 0.18µm CMOS
S. Andersson (Linkoping University), I. Carlson (Linkoping University), S. Natarajan ( Emerging Memory Technologies Inc/ Linkoping University), A. Alvandpour Linkoping University)
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